1. Field of the Invention
The present invention relates to a microcontroller that operates in synchronism with the system clock, and fetches, decodes and executes an instruction program on a memory such as a ROM by pipeline processing.
2. Prior Art
When a fresh look is taken at a system using a microcontroller from the viewpoint of power consumption reduction, not all tasks require that the microcontroller operate at the highest frequency. It is necessary only that the microcontroller operate at the lowest operating frequency that does not degrade the performance of the system.
With such a case in mind, typical microcontrollers are structured so that the division ratio can be changed in the process of generating the system clock from the original oscillation signal.
Many conventional microcontrollers control the division ratio by setting given data into an address-mapped register. In the case of this structure, since a time loss corresponding to the instruction execution cycle for writing occurs even if power consumption and the operating frequency are finely controlled, there are cases where the intended frequency control and power control effects cannot be obtained. As a measure against these problems, some microcontrollers change the frequency in accordance with the memory space that they access (for example, see Japanese Laid-Open Patent Application No. H02-118811). However, this is not a complete solution to the problems because it is necessary to execute an instruction to jump to the memory space allocated to the frequency to be changed.
A conventional microcontroller as described above will be described. FIGS. 10 and 11 are block diagrams showing the schematic structure of the conventional microcontroller. FIG. 10 shows in detail the structure of a clock generator in the microcontroller. FIG. 11 shows in detail the structure of a CPU in the microcontroller.
In FIG. 10, reference numeral 1000 represents the microcontroller, and reference numeral 100 represents the CPU. The CPU 100 is connected to a ROM 700 through a bus. With a clock generator 800, the CPU 100 not only is connected through a bus but also receives a system clock sysclk from the clock generator 800. The microcontroller 1000 operates in synchronism with the system clock sysclk. The clock generator 800 with the original oscillation signal oscin as the input comprises a clock division circuit 801, a selector 802, a clock division control circuit 803 and a clock division control register 804. The clock division circuit 801 divides the original oscillation signal oscin to generate a plurality of signals of divided oscillation clock cycles as well as a signal of the oscillation clock cycle. The clock division control register 804 is a register where reading and writing can be performed by instructions processed by the CPU 100, and holds information for selecting one of the signals of the divided oscillation clock cycles generated by the clock division circuit 801 based on the set data. The clock division control circuit 803 adjusts the clock switching timing based on the data set in the clock division control register 804, and outputs a control signal oscsel of the selector 802. The selector 802 selects one of the signals of the divided oscillation clock cycles outputted from the clock division circuit 801 in accordance with the control signal oscsel, and transmits it to the CPU 100 as the system clock sysclk.
In FIG. 11, the CPU 100 comprises an instruction decoder 400, a data path 300, a data register 500, an address register 600, and a bus interface 200. Data exchanges in the CPU are performed through the bus interface 200, and the operation of the CPU is controlled by a microcode (MIR).
Next, the typical operation of the microcontroller structured as described above will be described with an 8-bit microcontroller as an example.
First, the data inputted from the ROM 700 passes through the bus interface 200, is fetched into an instruction fetch buffer (IFB) 401 in the instruction decoder 400, passes through an instruction buffer (IB) 402, and then, is divided into an operation code and an operand.
The operation code outputted from the IB 402 is inputted to an instruction register (IR) 403, decoded by a programmable logic array (PLA) 404, and then, supplied as the microcode MIR to each of the following constituent blocks: the bus interface 200; the data path 300; and the instruction decoder 400. These constituent blocks perform the processing in accordance with the inputted microcode MIR.
The operand outputted from the IB 402 is transmitted to the data path 300, the data register 500, the address register 600 or the like in accordance with the microcode MIR.
To change the division ratio of the system clock sysclk, by writing a set value corresponding to each division ratio into the address-mapped clock division control register 804, the switching timing is adjusted by the clock division control circuit 803, the selection signal oscsel is outputted to the selector 802, and in accordance therewith, the selector 802 selects a signal of a divided oscillation clock cycle and transmits it to the CPU 100 as the system clock sysclk.
The operation of the conventional microcontroller as described above will be described by use of a program example and a timing chart.
FIGS. 12A, 12B and 12C show an instruction format, the program example and the operation timing chart of the conventional microcontroller, respectively. The circled numerals in FIGS. 12B and 12C are replaced with (1) to (7) in the following description:
The instruction format comprises a 4-bit extension code representative of the page number of the instruction map, an 8-bit operation code, and a 4×n-bit (n=1,2, . . . ) operand.
The program example executes instructions (1) to (7). The program example first executes the instruction (1) with the system clock sysclk as a signal of the oscillation clock cycle of the original oscillation signal oscin, and then, switches the division ratio from the oscillation clock cycle to the oscillation clock cycle divided by two by the instruction (2). Then, after executing the instructions (3) and (4), the program example returns the division ratio to the oscillation clock cycle by the instruction (5), and executes the instructions (6) and (7). Of the reference designations shown in the timing chart, (1)-1 represents the machine code of the first nibble of the instruction (1) of the program example, and (1) μ-1 represents the first cycle of the execution cycle of the instruction (1). T1 and T2 represent the timings of the falling and rising edges of the system clock sysclk, respectively.
Since the selection signal oscsel is low at the timing A, the system clock sysclk operates in the cycle of 1/1 oscin (signal of the oscillation clock cycle). The IFB 401 and the IB 402 fetch the instructions (1)-1 and (1)-2 from the ROM 700 at T1. Since the instruction (1)-1 is an extension code and (1)-2 is the first nibble of the operation code and not an operand, the data are all outputted to the IR 403. At the timing B, the IR 403 latches (1)-1 and (1)-2 at T2 and outputs them to the PLA 404, and the PLA 404 starts decoding. Since (1)-1 is an extension code and (1)-2 is not processed until the second nibble of the operation code is fetched, at the timing C which is the next T1, only the microcode MIR ((1) μ-1) corresponding to (1)-1 is outputted as an extension code recognition cycle. At the same time, the IFB 401 fetches the instructions (1)-3 and (2)-1. At the timing D, the operation code (1)-3 of the remaining one nibble of the instruction (1) is fetched into the IR 403, and decoded by the PLA 404 together with (1)-2 waiting to be processed. At the timing E, the microcodes MIR ((1)μ-1) of (1)-2 and (1)-3 are outputted, and (2)-2 and (2)-3 are fetched into the IFB 401. Moreover, (2)-1 that is not fetched into the IR 403 at the timing D shifts to the IB 402 at the timing E. When passing through the IFB 401 and the IB 402 like (3)-1, the extension code is not fetched into the IR 403 at the timing F since it is recognized while passing through the IFB 401 and the IB 402, and (3)-2 and (3)-3 which are operation codes are fetched into the IR 403.
By the instruction (2), the selection signal oscsel becomes high at the timing G by the writing into the clock division control register 804 in the execution cycle (2) μ/3 to change the system clock sysclk from 1/1 oscin (signal of the oscillation clock cycle) to 1/2 oscin (signal of the oscillation clock cycle divided by two). Likewise, by the instruction (5), the system clock sysclk is returned from 1/2 oscin to 1/1 oscin.
As described above, the conventional microcontroller is capable of controlling the frequency by an instruction to perform writing into the clock division control register 804.
However, in the conventional microcontroller as described above, to change the frequency, several cycles are required for executing the instruction to perform writing into the register. This makes it impossible to finely adjust power consumption by the frequency control while maintaining the performance of the system.